› Forums › IoTStack › News (IoTStack) › Chip Aging Becomes Design Problem
Tagged: EdgeFog_G7, FPGA_H3
- This topic has 1 voice and 0 replies.
-
AuthorPosts
-
-
September 1, 2018 at 5:14 am #24314
#News(IoTStack) [ via IoTForIndiaGroup ]
“Semiconductor devices age over time, we all know that, but what is often not well understood are the mechanisms for aging or the limits that will cause a chip to fail,” says Stephen Crosher, CEO for Moortec. “In addition, there is bound to be a requirement for a minimum lifetime of a device, which will depend on the application. This could be 2 or 3 years for a consumer device, and up to 10 years for telecommunications devices. Given that aging processes are complex and often difficult to fully predict, many chip designs today are often over-designed to ensure adequate margin to meet requirements for reliable lifetime operation.”
The types of devices that demand high reliability are growing. “The advanced node devices that go into a base-station or into a server farm have pretty stringent reliability requirements,” points out Art Schaldenbrand, senior product manager at Cadence. “They operate 24 hours a day, 7 days a week. That is continuous stress. Then there are mission critical applications. A lot of focus on automotive, but that is just like industrial applications, or space applications where the cost of failure is very high. Once a satellite is sent into space, you want it to work until the end of its useful lifetime.”
What makes this all the more troubling is that some failure modes are statistical. “If aging processes could become more deterministic, or better still if you can monitor the aging process in real-time, then you can reduce the over-design,” says Crosher. “You could develop chips that react and adjust for aging effects, or even predict when chip failure may occur.”
-
-
AuthorPosts
- You must be logged in to reply to this topic.