Design Flow for a Custom FPGA Board in Vivado and PetaLinux

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Design Flow for a Custom FPGA Board in Vivado and PetaLinux
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The most error-proof method I have personally found to go about this is that I select the option to allow for Vivado to manage the HDL wrapper, then create my own module in Project Manager by selecting ‘Add Sources’ → ‘Add or Create Design Source’ and I simply copy+paste the instantiation from the auto-generated wrapper file into my own.
I then set my own file as the new top level file for the design and disable (NOT delete) the wrapper auto-created by Vivado.
If I need to update the block design, I re-enable the auto-created HDL wrapper and set it back as the top before going into the block design to modify it.
The hardware settings is where the kernel is configured to boot from the SD card for this design.
With everything configured in the kernel and root file system settings, the next thing to do is build out the device tree.
With everything configured and the device tree built, the project needs to be built which will call all of the various compilers needed to create the final output files for the kernel image and root file system.
Since the ZynqBerry will be booting from an SD card, the only things that need to be packaged into the boot image file are the normal first stage bootloader (NOT the one for JTAG bring up), FPGA bitstream, and u-boot.
If the board were being booted from some sort of on-board memory, then this boot image file would also include the kernel, device tree, and root file system.
Now that the boot image file is loaded into the FPGA’s flash memory to point to the rest of the boot process to the SD card, the SD card needs to be prepped accordingly.
For this design in particular, since the ZynqBerry is being booted from the SD card, u-boot needs to have the block number of the SD card configured into it for where to load the device tree and kernel from

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